1. Field of the Invention
The present invention relates to a semiconductor device obtained by stacking a plurality of semiconductor chips and a method of manufacturing the same, as well as a structure obtained by stacking a plurality of semiconductor wafers.
2. Description of Related Art
A multichip module (MCM) is known as a highly integrated and highly functionalized semiconductor device.
In a typical conventional multichip module, a plurality of semiconductor chips are arranged in line on a substrate and connected with one another by wires, for example. In recent years, a multichip module obtained by stacking a plurality of semiconductor chips on a substrate and connecting the semiconductor chips with one another by wires thereby implementing miniaturization (reduction of a mounting area) has been provided.
In such a structure, the number of the wires connecting the semiconductor chips with one another is increased as the number of the semiconductor chips or the degree of integration of the semiconductor chips is increased. In general, pads to which end portions of the wires are bonded are aligned on peripheral edge portions of the surfaces of the semiconductor chips. Each wire is provided to extend over the peripheral edge portions of a pair of semiconductor chips. In order to avoid contact between the wires and prevent contact between the wires and capillaries holding the wires when bonding the same to one another, therefore, not less than constant intervals must be provided between the pads adjacent to one another. Therefore, the number of the pads arrangeable on each semiconductor chip (the number of connectable wires) is limited, and the number of the semiconductor chips or the degree of integration thereof cannot be increased beyond the limit. Further, influences exerted by the impedances of the wires cannot be eliminated, and the speed of data transmission between the semiconductor chips and the operating speed cannot be increased. In the structure of the conventional multichip module, therefore, high integration, high functionalization and increase in the operating speed are limited.
In order to implement higher integration, higher functionalization and a higher operating speed of the semiconductor device, a technique of connecting the semiconductor chips with one another by through silicon vias (TSVs) is now in the process of development. The through silicon vias pass through the semiconductor chips (silicon chips) in the thickness direction thereof. Each semiconductor chip is provided with a plurality of through silicon vias. A bump is arranged on the forward end of each through silicon via. A plurality of semiconductor chips are stacked on a substrate, and bumps arranged on the upper surface of each semiconductor chip and those arranged on the lower surface of a semiconductor chip opposed to the semiconductor chip from above are bonded to one another, thereby connecting the semiconductor chips with each other.
In the structure employing the technique, the through silicon vias can be provided in a larger number than the wires as compared with the structure obtained by connecting the semiconductor chips with one another by the wires, and hence the number of the semiconductor chips can be increased, thereby attaining higher integration and higher functionalization. Further, the through silicon vias can be provided in the number larger than that of the wires, whereby the quantities of data transferred between the semiconductor chips can be increased. In addition, the length of the through silicon vias is smaller than that of the wires, whereby the operating speed of the semiconductor device can be improved (increased).
FIGS. 3A to 3O are schematic sectional views successively showing steps of manufacturing a semiconductor device having semiconductor chips connected with one another by through silicon vias.
The semiconductor device having the semiconductor chips connected with one another by the through silicon vias is manufactured in a state of a semiconductor wafer obtained by aggregating a plurality of semiconductor chips.
As shown in FIG. 3A, the front surface of another semiconductor wafer W102 is opposed to the front surface of a semiconductor wafer W101. A plurality of bumps 101 and a plurality of bumps 102 are formed on positions of respective front surfaces of the semiconductor wafers W101 and W102 opposed to one another respectively. Then, the semiconductor wafer W102 is approximated to the semiconductor wafer W101, and the bumps 102 of the semiconductor wafer W102 are brought into contact with the bumps 101 of the semiconductor wafer W101 respectively. Thus, the semiconductor wafer W102 is supported on the semiconductor wafer W101 with a small interval.
Then, underfill (liquid resin) is injected into the space between the front surfaces of the semiconductor wafers W101 and W102, as shown in FIG. 3B.
Thereafter the rear surface of the semiconductor wafer W102 is polished, as shown in FIG. 3C.
When the semiconductor wafer W102 reaches a prescribed thickness, through silicon vias 103 passing through the semiconductor wafer W102 in the thickness direction are formed on the same positions as the bumps 102 in plan view respectively, as shown in FIG. 3D. More specifically, holes passing through the semiconductor wafer W102 are formed on the same positions as the bumps 102 of the semiconductor wafer W102 in plan view respectively by photolithography and etching. Then, insulating films made of silicon oxide (SiO2) are formed on the inner surfaces of the holes by thermal oxidation or CVD (Chemical Vapor Deposition). Thereafter the holes are filled up with the material for the through silicon vias 103, whereby the through silicon bias 103 are formed to pass through the semiconductor wafer W102 in the thickness direction.
Then, bumps 104 are formed on the through silicon vias 103 respectively, as shown in FIG. 3E.
Then, the front surface of still another semiconductor wafer W103 is opposed to the rear surface of the semiconductor wafer W102, as shown in FIG. 3F. Bumps 105 are formed on positions of the front surface of the semiconductor wafer W103 corresponding to those of the bumps 104 provided on the rear surface of the semiconductor wafer W102 respectively. Then, the semiconductor wafer W103 is approximated to the semiconductor wafer W102, and the bumps 105 of the semiconductor wafer W103 are brought into contact with the bumps 104 of the semiconductor wafer W102 respectively. Thus, the semiconductor wafer W103 is supported on the semiconductor wafer W102 with a small interval. Thereafter underfill is injected into the space between the rear surface of the semiconductor wafer W102 and the front surface of the semiconductor wafer W103.
Thereafter steps of reducing the thickness of the semiconductor wafer W103 by polishing the rear surface thereof (a step corresponding to that shown in FIG. 3C), forming through silicon vias 106 in the semiconductor wafer W103 (a step corresponding to that shown in FIG. 3D), forming bumps 107 on the through silicon vias 106 respectively (a step corresponding to that shown in FIG. 3E), bonding the front surface of a further semiconductor wafer W104 to the rear surface of the semiconductor wafer W103 (a step corresponding to that shown in FIG. 3F), reducing the thickness of the semiconductor wafer W104 by polishing the rear surface thereof (a step corresponding to that shown in FIG. 3C), forming through silicon vias 108 in the semiconductor wafer W104 (a step corresponding to that shown in FIG. 3D) and forming bumps 109 on the through silicon vias 108 respectively (a step corresponding to that shown in FIG. 3E) are carried out. As a result, a structure shown in FIG. 3G is obtained.
Then, the front surface of a further semiconductor wafer W105 is opposed to the rear surface of the semiconductor wafer W104, as shown in FIG. 3H. Bumps 110 are formed on positions of the front surface of the semiconductor wafer W105 corresponding to those of the bumps 109 provided on the rear surface of the semiconductor wafer W104 respectively. Then, the semiconductor wafer W105 is approximated to the semiconductor wafer W104, and the bumps 110 of the semiconductor wafer W105 are brought into contact with the bumps 109 of the semiconductor wafer W104 respectively. Thus, the semiconductor wafer W105 is supported on the semiconductor wafer W104 with a small interval. Thereafter underfill is injected into the space between the rear surface of the semiconductor wafer 104 and the front surface of the semiconductor wafer W105.
Thereafter the rear surface of the semiconductor wafer W105 is polished, as shown in FIG. 3I.
When the semiconductor wafer W105 reaches a prescribed thickness, through silicon vias 111 passing through the semiconductor wafer W105 are formed on the same positions as the bumps 110 in plan view respectively, as shown in FIG. 3J. Then, bumps 114 are formed on the through silicon vias 111 respectively.
Thereafter a glass plate 112 is bonded to the rear surface of the semiconductor wafer W105, as shown in FIG. 3K.
Then, the rear surface of the semiconductor wafer W101 is polished on the basis of the glass plate 112, as shown in FIG. 3L.
When the semiconductor wafer W101 reaches a prescribed thickness, dicing tapes 113 are bonded to the rear surface of the semiconductor wafer W101, as shown in FIG. 3M.
Thereafter the glass plate 112 is removed from the rear surface of the semiconductor wafer W105, as shown in FIG. 3N.
Then, the structure including the semiconductor wafers W101 to W105 is divided by dicing blades 115 into semiconductor devices each having semiconductor chips connected with one another by through silicon vias, as shown in FIG. 3O.
According to the manufacturing method, however, the dicing blades 115 come into contact with the semiconductor wafers W101 to W105 in the dicing. Therefore, force is directly applied from the dicing blades 115 to the semiconductor wafers W101 to W105, to chip or crack corner portions of the semiconductor chips (the semiconductor wafers W101 and W105). Further, the dicing blades 115 cut the multilayer structure of the semiconductor wafers W101 to W105 and the underfill, and hence the corner portions of the semiconductor chips are particularly easily chipped or cracked.
In a semiconductor device manufactured according to the manufacturing method, further, corner portions of the semiconductor chips may be damaged by chipping or cracking due to contact with a hand, not only in the dicing but also in handling.